The present invention relates to a PLL (phase-locked loop) oscillator circuit which applies a phase-locked loop to control an oscillator of the microwave band.
In general, in microwave oscillators for use in a receiver for SHF (superhigh frequency) broadcasts, microwave communication apparatus, and the like, it is desired that the variation of the oscillation frequency as a result of temperature changes be small, that the levels of spurious signals be low and that a sharp oscillation spectrum with little residual FM noise be afforded. Heretofore, in receiving a downlink signal of 3.7-4.2 GHz from a satellite during satellite communication, a PLL oscillator circuit as shown in FIG. 1 has been adopted as a local oscillator of 2.94 GHz for frequency conversion, but it has been unsatisfactory.
Referring to FIG. 1 illustrative of a prior art device, a signal from a reference signal generator 1 employing a crystal oscillator is applied to a phase comparator 10 through frequency dividers 8 and 9 as a reference signal. The signal from the reference signal generator 1 is also applied to a frequency multiplier 2 to have its frequency multiplied by n. The multiplied signal is applied to a mixer 3, which is also supplied with a signal from a voltage-controlled oscillator 4 (hereinafter, abbreviated to "VCO"). The mixer 3 functions to convert the applied signals into a signal of a frequency equal to the difference between the frequencies of both the input signals. Unnecessary signal components are excluded through a band-pass filter and amplifier 5 (abbreviated to "BPF.multidot.AMP") selectively amplifies a desired signal component. The signal from the BPF.multidot.AMP 5 is applied to the phase comparator 10 through frequency dividers 6 and 7.
The phase comparator 10 compares the phases of the applied signals, and provides a signal corresponding to the phase difference. The signal from the phase comparator 10 is applied to a low-pass filter and amplifier 11 (abbreviated to "LPF.multidot.AMP"). The resultant signal from the LPF.multidot.AMP 11 is applied to the VCO 4 to control the oscillation frequency thereof. The PLL oscillator circuit is constructed as thus far described. Assuming that the oscillation frequency of the reference signal generator 1 is 74.904459 MHz and that the frequency multiplication ratio of the frequency multiplier 2 is 39, the output frequency of the BPF.multidot.AMP 5 becomes 18.726115 MHz. Also, assuming that the frequency division ratios of the frequency dividers 6 and 7 are 4 and 256, respectively, and that the frequency division ratios of the frequency dividers 8 and 9 are 4 and 1,024, respectively, the phase comparison frequency of the phase comparator 10 becomes approximately 18 kHz.
With such prior art, when viewed over a long time, the frequency stability of the VCO 4 is substantially equal to the precision of the crystal oscillator because the control of the phase-locked loop is dependent upon the precision of the reference signal generator 1. However, the residual FM noise which is the frequency stability as viewed for a short time is determined by the residual FM noise characteristics of the VCO 4 itself in the case where the control voltage of the VCO 4 is fixed. This signifies the disadvantage that, in spite of the phase-locked loop control, the frequency stability cannot be made better than the residual FM noise characteristics of the VCO 4 itself.
When the LPF.multidot.AMP 11 has the passing band width thereof broadened to pass even the noise frequency of the residual FM noise, and the control time of the phase-locked loop is shortened so that even the noise frequency may be responded to, the residual FM noise decreases. This measure, however, results in increasing a control on the VCO 4 and subjecting the VCO 4 to the FM modulation with the reference signal of the phase comparator 10, so that a phase-locked loop control of good FM noise characteristics cannot easily be made.